The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, conventional FinFET devices may still have certain drawbacks. For example, due to lateral growth of epitaxial source/drain features of the FinFET devices, increased distances between neighboring fins may be required in order to avoid shorting with neighboring FinFET devices. In high density static random access memory (SRAM) cells where the distances between neighboring fins may be a dominant factor in determining cell density, the increased distances between neighboring fins may limit the density of the SRAM cells. For further example, the same substrate may include FinFETs using different numbers of fins, or regions having different density requirements, and epitaxial growth control of the source/drain features for FinFETs can be challenging.
Thus, existing techniques have not proved entirely satisfactory in all respects.